Two Papers on c · rcuit Extraction

"'.his paper describes thc algorithms. implementation, and performance of a hierarchical circuit extractorfor NMOS designs. The input to the circuit extractor is a description of the layout of the chip. and its outputis a hierarchical wirelist describing the circuit. The extractor is divided into two parts, a front-end and aback-end. The front-end analyzes the CIF description of a layout and partitions it into a set of non-overlapping rectangular regions called windows: redundant windows are recognized and are extracted onlyonce. The back-end analyzes each unique window found by the front-end. The back-end determines theelectrical circuit represented by the window, and computes an interface that is later used to combine the-window with others that are adjacent. The paper also presents a simple analysis of the expected performanceof the algorithm, and the results of running the extractor on some real chip designs.